Proposal Details
While trying to implement SVE for the ARM64 assembler backend, we've been trying to come up with a consistent way of representing registers and all of their possible extensions.
For example, currently certain bits are toggled in the register number to signal that the register has an index suffix, or some bits are used to store the vector lane size (e.g. B/H/S/D).
We've worked out that there won't be enough space in the int16 passed into the Rconv function to be able to print the register accurately with just this information as there are a lot of combinations of registers and extensions. This mainly causes an issue in the DConv function - we aren't able to convert all of our register possibilities to a string.
Therefore I propose we implement a workaround for Rconv so that our backend can use the rest of the fields in the Addr structure for extra type information.
One way of doing this without breaking other architecture implementations would be to add another register-to-string function that the backend can register globally. Then in writeDConv we can check p.Ctxt.Arch.Family for the current architecture being compiled and search a table of register handlers keyed by this value. This handler will write the name of the register if one is available, otherwise it will fall back to the original logic. This would be opt-in and backwards compatible, so I would suggest this over refactoring Rconv to accept an Addr structure.
Comment From: gopherbot
Change https://go.dev/cl/599315 mentions this issue: cmd/internal/obj: Add a new handler for register printing from Addr
Comment From: snickolls-arm
I've written this patch to demonstrate the code changes that this would involve.
Change https://go.dev/cl/599315 mentions this issue:
cmd/internal/obj: Add a new handler for register printing from Addr
Comment From: cherrymui
This is an implementation detail as there is no public API changes. There is no need for a proposal. We can just discuss on the CL. Thanks.